A phase-locked loop is a circuit including a voltage controlled oscillator (VCO) which is designed to control the VCO to generate an output signal having a predetermined frequency and/or phase relationship with a reference signal. A typical phase-locked loop is shown in FIG. 1.
The phase-locked loop comprises an oscillator 101. The output of the oscillator is output from the phase-locked loop circuit on line 105. Additionally, the output of the oscillator 101 is fed via a divider 104 to an input of a phase/frequency detector (PFD) 102. The PFD 102 outputs a signal that is representative of the phase and/or frequency difference between a reference signal on line 106 and the signal output from the oscillator. The PFD output signal is filtered at a low pass filter 103. The output of the low pass filter 103 on line 107 is a voltage control signal that is suitable for use in controlling the oscillator to tune its resonant frequency to match the frequency of the reference signal.
Except for the VCO, the components of the phase locked-loop are suitably operable in the digital domain. The voltage tuning signal 107 output by the low pass filter 103 is a digital signal. The VCO operates in the analogue domain. In typical phase locked-loops the digital voltage tuning signal is input to a digital to analogue converter (DAC) 108. The DAC outputs an analogue voltage tuning signal on line 109. This analogue voltage tuning signal is applied to the oscillator. Suitably the oscillator comprises an inductor and a variable capacitor connected in parallel. The analogue voltage tuning signal is applied directly to the variable capacitor to modify the value of the capacitance of the capacitor.
On application of a current, the inductor and capacitor generate an oscillating signal at their resonant frequency, given by:f=1/2π√{square root over (LC)}  (equation 1)where f is the resonant frequency, L is the inductance of the inductor and C is the capacitance of the capacitor. Standard units apply. In accordance with this equation, modifying the capacitance, C, modifies the resonant frequency of the oscillating signal.
A problem with the phase-locked loop of FIG. 1 is that the voltage tuning signal picks up noise as it passes through the DAC. It is therefore preferable to tune the oscillation frequency of the oscillator without having to convert the digital tuning signal to an analogue tuning signal.
EP 1143606 describes a mechanism for tuning the oscillation frequency of a VCO directly using a digital tuning signal. The VCO comprises a crystal resonator connected to two capacitor banks. Each capacitor bank includes a number of capacitors connected to the resonator via switching devices. The oscillation frequency of the VCO depends on the capacitance provided by the capacitor banks. The capacitance of each capacitor bank is selected by enabling or disabling the switching devices connected to the capacitors in dependence on a digital tuning signal applied from the phase-locked loop. If the desired capacitance can not be achieved by enabling a combination of the capacitors in the bank, then a sigma delta modulator is additionally employed. The sigma delta modulator enables one capacitor in the capacitor bank for a portion of a clock cycle and disables it for the remaining portion of the clock cycle. Over time, the capacitance of that capacitor averages to a value that is less than its instantaneous value. The ratio of the time for which the capacitor is enabled to the time for which the capacitor is disabled can be adjusted such that the desired fractional capacitance is achieved. The capacitance of the capacitor banks can therefore be fine tuned so that the oscillation frequency is matched to the reference frequency.
One problem with this mechanism is that the capacitors in the capacitor banks need to be initially very accurately calibrated in order that they can be used to precisely tune the oscillation frequency.
There is a need for an improved design for digitally controlling a VCO which has the advantage of enabling precise tuning of the oscillation frequency without the disadvantage of requiring extensive initial calibration. Additionally, there is a need for a design which is suitable for integration onto a single chip.